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Design for Test and Verification introduced by ISLI
19 September 2002
September 19, 2002. The Institute for System Level Integration announced the launch today of two new modules for its world leading masters course in System Level Integration. The modules – Design for Testability and Verification – have been produced to tackle two of the hottest issues in System on Chip design.
“Verification and Design for Test are two of the most challenging issues in the industry today,” commented Avril Manners, Distance Learning and MSc Director at the ISLI. “At the Institute we want to be as responsive as possible to industry needs, and these units will help us continue to be at the leading edge of developing the design skills of the future.”
The new units are available to full and part-time students studying at the Institute, which is based on the Alba Campus in Livingston, Scotland. They will also be available to distance learning students studying for an online Masters Course.
The online Masters course – the first in the world – was launched in March 2002. The two new units join Introduction to Hardware Design Automation, Introduction to Embedded Software, VLSI Design, Embedded Software I (SoC) and Microcontrollers and Microprocessors.
Semiconductor Design for Testability aims to introduce Design for Test concepts in relation to semiconductor devices and Ics. Emerging design practices and standards are reviewed, and on completion, students will be able to understand the constraints and motivations behind DfT integration as well as having the knowledge to participate in a DfT integration product in both digital and mixed signal domains. It has been developed, and will be delivered in cooperation with the Centre for Microsystems Engineering at Lancaster University.
Introduction to Verification provides students with a good basic knowledge of VLSI functional verification methodologies, allowing them to become useful members of a verification team. The emphasis in this module is on the practical aspects of the planning and execution of functional verification of complex digital ASIC/FPGA designs.
The modules will be available for students in Autumn of this year. Initial interest can be registered with jenny.honey@albacentre.co.uk
Institute
for System Level Integration
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